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Miniaturization 

One of AES’s specialties is miniaturization, bringing long years of know-how and experience.

We Miniaturize for different purposes: saving landscape and provide smallest modules in the world for different markets, providing off load, low power consumption, low Total Cost of Ownership (TCO), whereas for most cases at least one of these benefits, will bring about the need to miniaturize.

Miniaturization technologies:

 

High Density Substrates

Thin trace width / Vias

 

Layer thickness 100um - 10um

 

Optimized power dissiption

Signal / Power Integrity

Lower thermal resistance and parasitic
(full control on the Z axis) 


Manipulation over wafer:

Add RDL (redistribution layer) - for FC or CSP

Back Grind

PoP / CoC

3D interconnection and packaging

 

Integrated Passive Devices (IPD)

 

Integrated Active Devices (IAD)